Print-out control systems



Dec. 5, 1967 c. H. PROPSTER, JR

PRINT-OUT CONTROL SYSTEMS 5 Sheets-Sheet L',

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SYSTEMS FRINT'UUT CONTEUL 3 Sheets-Sheet ...WMI l Q ...Nl Q www ...m .QQ.. Q.. Q.. QS QQ. QQ. QQ. QQNQ. NQ@ .QT F l QQ.. S QQ@ 1 e /f Q Q Q QQJQQ Q Q Q. Q Q Q Q. Q |I C .w Q w Q .WQ Y .QN :QN .QN .Q wml @Q Q. bmxNNN .mmh Nwk NNN :QQ w QW 13% www ...www QE. .www F W Q QQN QQ@ QQN HQ Q@y Q QW QQN .QQN .EN .w L w Q w Q u Q Q. Q QQ ,QQ Q .QQ .QQ QQ QQ HQQ QQQ .NQ s N l MINI 111.1-- :i .QLSSQQ if .NQN .QQN .QQN .N ..TII QQQQQ-w. fl Q .IH ;&- HfIl QQ .QE www .QQ NFS .QQQ .Q -I D l Qk. .QQ E! Il.QQQNQQQT 1.1.1 QQQQXQQQ .QQQSLQQ f rL QTEL QQQQN .NNE .EN .QQN .QQQN .NTQQ fi I QN1 QQQN ATTORNEY Unitecl States Patent O M 3,356,997 PRINT-OUTCONTROL SYSTEMS Charles H. Propster, Jr., San Jose, Calif., assignor toGeneral Electric Company, a corporation of New York Continuation ofapplication Ser. No. 204,698, June 25, 1962, which is a division ofapplication Ser. No. 849,002, Oct. 27, 1959, now Patent No. 3,093,730,dated June 11, 1963. This application June 21, 1966, Ser. No. 559,342

Claims. (Cl. S40-172.5)

ABSTRACT OF THE DISCLGSURE Control apparatus for transmitting digitsstored in a memory device in a predetermined order to a utilizationdevice in the inverse order. A counter is incremented as successivestorage locations containing digits of successively increasing orders ofsignicance are scanned, a digit of predetermined significance beingtransferred to the utilization means as its corresponding storagelocation is identitied by a predetermined count in the counter. Logiccircuitry resets the counter after each transfer and provides an extraincrementation so that the predetermined count is reached as memorylocations containing successively lower-order digits are scanned,permitting transfer of digits of successively lower significance to theutilization device.

This application is a continuation of application Serial Number 204,698,filed June 25, 1962 and now abandoned, which application is a divisionof application Serial Number 849,002, tiled October 27, 1959, and issuedJune 11, 1963 as patent 3,093,730.

This invention pertains to a print-out control system and, moreparticularly, to a control system for presenting groups of numericalcharacters stored on a rotating magnetic medium to a printer in such amanner that, although the characters in a given group which representnumerical data are accessible in increasing order of significance, thecharacters are printed out in decreasing order of significance in orderthat all characters of each group may be sequentially printed on a linein decreasing order of significance and all zeroes in orders of highersignicance than the most significant non-zero character of a group maybe suppressed.

In data accumulating systems and other similar data processing systemsutilizing a magnetic drum, or other types of recirculating memorydevices, it is convenient to store numerical data in series beginningwith the least significant character of a group representing a number inorder that the data may be read out and processed in a serial manner andin increasing order of significance, thereby facilitating thepropagation of binary and decimal carries. However, upon printing outdata stored and processed in that manner, it is desirable to read outand print groups of characters representing numbers in inversesequential order in order that a typewriter, or other recording device,may be employed to print the numbers on a line in successive spaces fromleft to right. That is desirable in order to avoid the complexelectromechanical control otherwise necessary to print characters insequential order from right to left and in order to facilitate thesuppression of all zero characters of a group representing numbers thatare in numerical orders of greater significance than the mostsignificant nonzero character.

Accordingly, it is an object of this invention to provide a novelcontrol system for printing out numerical data stored in a recirculatingmemory device, such as a rotating magnetic drum.

It is another object of this invention to provide an improved dataoutput control system.

3,356,997 Patented Dee. 5, 1967 It is a further object of this inventionto provide a control system for transmitting information stored in amemory device in a predetermined order to a utilization means in theinverse order.

As described in U.S. Patent 3,093,730, issued June ll, 1963 and assignedto the assignee of the present invention, inspection data from aplurality of sensors displaced along a tinplate inspection line may beaccumulated and printed on a permanent record through a plurality ofsynchronizing channels, one channel for each different type ofinspection data. Certain channels include a delay element between itsassociated sensor and accumulator to compensate for the distance thesensor is displaced from a reference point along the inspection line inorder that all inspection data accumulated at a given time pertain tothe same item, or foot of tinplate, inspected at different times.

A single rotating magnetic drum provides all of the binary storagerequired to implement both the shift registers employed as delayelements and the accumulating registers. Only a small amount ofadditional binary storage is necessary for the control circuits of eachtype of register. That additional binary storage is relatively small asonly one control circuit is provided for all of the registers of eachtype. This economic use of control circuits is accomplished through atime-sharing technique made feasible by organizing the drum into equalparts such that at least one operating cycle is provided for eachregister during each drum revolution.

Data recorded on part of a track on the magnetic drum is read out inseries and immediately re-recorded in corresponding cells of anotherpart of the track. Part of a drum cycle later, the data is re-read andtransferred back to the rst part. Thus, the data is continuallytransferred between the equal parts of the track. Each time the data istransferred, it may undergo some operation; therefore, a systemimplemented in such a manner may perform as many as two operationsduring one drum revolution or cycle. The operation is a shift operationin the case of the shift registers implemented on one track and anarithmetic operation for the accumulating registers implemented onanother track.

At the conclusion of a data accumulating period, such as at the end ofthe inspection of a given coil of tinplate, the inspection data istransferred to a plurality of buter registers, each buffer registercorresponding to an accumulating register and being implemented on atrack of a rotating magnetic drum in a similar manner as thecorresponding accumulating registers. Therefore, the inspection data isread out and printed sequentially beginning with the most significantcharacter of the last buffer register read during a given one-half of adrum cycle until all of the data transferred into all of the bufferregisters has been printed out.

All of the data is printed on a sheet of paper from left to right in asingle line so that the most significant character of each group ofcharacters read from successive buffer registers appears on the left ofeach group. As the characters of a given group are sequentially read outfor printing, a control Hip-flop is set to inhibit the printing of eachsuccessive character until a nonzero character is read in response towhich the control ipop is reset to allow that nonzero character and allof the remaining characters of the group to be printed.

In accordance with the invention, the sequential printing of digits inthe order of most-significant to least-significant is efected undercontrol of a counter which is incremented by one as each sector of adrum track storing a digit is scanned by a transducer. The countercommences from an initial count of one so that a predetermined count isreached as the transducer is scanning the sector immediately precedingthe one containing the most-significant digit. At this time, if theutilization device is not ready to receive a digit, the counter is resetand again incremented by one for each sector scanned, commencing withthe sector containing the most-significant digit. If the utilizationdevice is ready to receive a digit, the digit is transferred and thecounter receives an extra incrementation while scanning the sectorcontaining the most-significant digit, causing the counter to have acount of two upon completion of scanning of the sector containing themost-significant digit. Thus, the predetermined count will next bereached while the transducer is scanning the sector preceding the onecontaining the next most-significant digit. In this manner, theaddressing of the sectors continues in inverse order frommost-significant to leastsignificant by providing an extraincrementation of the counter each time a digit is transferred to theutilization device.

The subject matter of the invention is particularly pointed out anddistinctly claimed in the concluding portion of the specification. Theinvention, however, both d as to organization and method of operationmay best be understood by reference to the following description takenin connection with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of the accumulating and output buffersections in a data accumulating system having a plurality ofaccumulators and corresponding output buffer registers implemented ontracks of a rotating magnetic medium;

FIG. 1a is a schematic diagram of the print-out control section;

FIG. 2 is a timing diagram of synchronizing pulses;

FIG. 3 illustrates schematically the physical location of recordedtiming pulses in each sector with respect to recorded index pulses whichdefine the sectors; and

FIGS. 4, 5 and 6 illustrate schematically the manner in which thesynchronizing pulses of FIG. 2 may be obtained.

For a detailed description of the complete data accumulating system ofwhich the present invention is a component part, reference is made tothe aforementioned copending application, Serial No. 849,002, from whichthe present application has been divided.

Circuit elements Before proceeding with a detailed descriptoin of anembodiment of the invention, circuits which may be used to implementthat embodiment will first be generally described. For a detaileddescription and diagrams of those circuits, reference is made to theaforementioned copending application. The basic module or building blockfrom which almost all of the circuits of the invention may beconstructed consists of a NOR-circuit comprising a common-emittertransistor amplifier that is useful not only as an inverter and as anactive element in transistor monostable multivibrators or one-shots andbistable multivibrators or p-tiops but also to provide the logic AND andOR functoins. The logic functions are provided with a NOR-circuit bycoupling an input terminal to the base of the transistor by impedanceelements so that only when both input signals are negative with respectto the emitter bias will the transistor amplifier conduct. If theemitter is connected to a bias source of +6 volts, a logic level of +6volts for the output signals is established. That +6 volt level may bearbitrarily defined as a binary 0.

The collector of the transistor is connected to an output terminal whichis clamped to ground by a diode so that a second logic level of (l voltdefined as a binary l is established. Accordingly, when two inputsignals A and B are both +6 volts, the signal at the output terminal isO volt. A Boolean equation for that logic AND function may be written asAB'=C. Since the output of the NOR- circuit employed as an AND-gate ischanged from a bit 0 to a bit l only in response to a +6 volt signal atboth input terminals, to obtain the logic AND function of any set ofsignals X and Y, the binary complements and Y are used as the inputsignals.

As noted hereinbefore, the NOR-circuit is also used as an OR-gate and asan inverter. For the logical OR function, both input terminals arenormally at +6 volts to hold the transistor cut off; the output terminalis then normally at 0 volt. If either input terminal is driven to Gvolt, the transistor conducts at saturation and the potential of theoutput terminal is driven to +6 volts. Thus, the output of the GR-gateis changed from a bit l to a bit 0 in response to a bit l signal ineither input terminal. The logic OR operation may be written as A+B=.Accordingly, the OR-gate operates on any set of signals X and Y toprovide as an output signal a bit 0 if either X or Y is a bit l. If onlyone input terminal is used, the logic element functions simply as aninverter.

A fiipfiop may be implemented by cross-coupling the output terminals oftwo NOR-circuits with their input terminals. A one-shot circuit may besimilarly implemented by using only a capacitor for the cross-couplingelement from the output terminal of one NOR-circuit to the inputterminal of the other.

It should be understood that these and other circuits employed, such aspower-drivers, write amplifiers and read omplifiers, may be implementedwith other conventional circuit congurations as long as it is understoodthat allowance should be made for the inherent inverting function ofeach NOR-circuit employed as either an AND-gate or an OR-gate if a logicgate of a circuit configuration not inherently providing inversion isemployed.

In the drawings, the AND-gate is represented by a half circle havinginput terminals coupled to it by small circles which represent theinherent inverting function of the NOR-circuit when employed to providethe logic function AB'=C. The OR-gate is represented by a half circlehaving input terminals running through it and an output terminal coupledto it by a small circle which represents the inherent inverting functionof the NOR-circuit when employed to provide the logic function A-i-Bz?.The other circuits are represented by block symbols bearing brief orabbreviated legends.

General description Three transducers or detectors (not shown) areprovided for sensing defects in tinplate as it is inspected and woundinto a coil by means also not shown. They are displaced from each othersuch that each inspects a different foot at a given time. Each defect,such as a pinhole, overgauge or undergauge, produces a pulse signal in acorresponding detector which is fed to a data input control circuit.

To coordinate all of the inspection data with respect to a given foot,the inspection data from each detector is so delayed in a delay sectionthat all of the data per taining to that given foot is fed to anaccumulating section at the same time. The delay section consists of thedata input control section and a plurality of drum shift regitserchannels. Each drum shift register channel receives its correspondingdata and transfers it through a plurality of binary storage cells, onecell at a time, in response to TACH pulses until the desired delay hasbeen introduced.

The TACH pulse source may be a tachometer driven by the tinplate andmodified to generate a pulse for each linear foot of tinplate thatpasses over it. Accordingly, the transfer of data through a drum shiftregister is controlled by TACH pulses and proceeds at the same rate thatthe tinplate is inspected. For instance, if the detectors arerespectively twenty-five, twenty-three and seventeen feet away from ashearing station, and if the data from the detectors is transferredthrough corresponding shift register channels having twenty-five,twenty-three and seventeen cells, respectively, all of the datatransferred out of the shift register channels at any given time mustpertain to the same foot of tinplate and that particular foot will atthat time have just passed the shearing station regardless of thetinplate speed.

Under normal operation, the tinplate is inspected at a relativelyconstant rate so that the TACH pulses are generated at a substantiallyconstant rate. However, when the tinplate coil is separated from theline, the tinplate is decclcrated, sheared and then accelerated by acontrol means not shown with the result that the TACH pulse repetitioinrate is first decreased and then increased to normal again. Since thedelay introduced by each drum shift register channel is controlled byTACH pulses, the delay through each channel is in terms of feet oftinplate inspected and the fact that the speed of the tinplate varies isnot important.

The accumulating section to which the coordinated data from the delaysection is fed consists of an accumulator input control circuit and aplurality of drum accumulators, one accumulator for each type of data tobe accumulated. The transfer of data from the drum shift registerchannels to the drum accumulators is accomplished through the data inputcontrol circuit and the accumulator input control circuit.

In transferring the inspection data from the delay section to theaccumulating section, the coordinated data may be processed to developother useful data to be accumulated. In the instant embodiment, all ofthe data pertaining to a given foot is processed by a logic circuit todetermine Whether any defects were detected. If there were none, asignal is developed indicating that the given foot is prime or first inquality. All of the prime-foot signals are accumulated in the samemanner as other data to provide the total number of prime feet in thecoil as part of the information record.

It may not be necessary to coordinate all of the data in certainapplications. Data which does not need to be coordinated is transferreddirectly through the data inputcontrol circuit and the accumulator inputcontrol circuit. In the instant embodiment, the total number of feetinspected and the total number of pinholes detected in the coil are notcoordinated. The total-feet data which is obtained by accumulating TACHpulses does not need to be coordinated since every foot of tinplate isthe same for the purpose of obtaining total footage.

The total-pinhole data is obtained by first counting pinhole defectsignals in the data input control circuit for each foot of tinplateinspected and then accumulating the pinhole count for every footinspected. If an exact total pinhole count is desired for each coil, thepinhole count data should also be coordinated in the same manner asother inspection data.

When a shear command is received from a source external to the system, atransfer switch is actuated and all of the data in the drum accumulatorsis transferred to a buffer section which includes a drum buffer and adata print control section. The drum buffer stores the accumulated datapertaining to the coil just sheared from the line until the data printcontrol section calls for it to be printed out, one digit at a time, ata rate determined by a printer.

The drum shift register channels, drum accumulatorsy and drum buffer 14are all implemented on a band of tracks on a magnetic drum so that onlyone source of synchronizing pulses is necessary for the proper timing ofthe operations in each section of the system. The source ofsynchronizing pulses is also implemented on the band of tracks in aconventional manner.

FIG. 2 is a timing diagram of the synchronizing pulses. The first graphis of the negative-going (-1-6 to 0 volts) index pulses IP, two of whichare oppositely written on a single track of the drum 18 (FIGS. 3 and 4)to separate it into two equal parts. Although in this embodiment thedrum 18 is divided into only two equal parts, it should be understoodthat the drum may be organized into any number of equal parts, by simplyproviding additional index pulses. For instance, the drum could beseparated into three equal parts. Data read from one part wouldimmediately be written in the next part. One third of a drum cyclelater, the data would be reread and rewritten in the third part. In thatway three operations could be performed in one drum cycle.

The third graph is of the negative-going (+6 to 0 volts) timing pulsesTP which are written on another track of the drum 18 (FIGS. 3 and 5).They separate each half of the drum between the index pulses into verysmall sectors, each sector constituting a single binary storage cell ina manner well known in the art. It should be noted from the graphs ofFIG. 2 and from the diagram of FIG. 3 that a blank space is left betweeneach index pulse IP and the tirst timing pulse TP following it. In theillustrated example that space is about 370 microseconds. The reason forit is to allow more than sufficient time for data to be transferredbetween sections of the system in synchronism with an index pulse beforeoperations within the sections commence and to provide at least oneblank timing pulse period (33*/3 microseconds). Thus, if desired, thatblank space may be reduced to forty microseconds for the time needed totransfer data between sections plus one timing pulse period.

In order to precisely control the transfer of data between sections andto accurately time operations within a given sections, several levels ofindexing and timing are provided by four index level pulses, each tenmicroseconds long, and live timing level pulses, each five microsecondslong.

The second graph of FIG. 2 is of the index level pulses derived from acircuit shown in FIG. 4 in response to an index pulse from a readamplifier 20. That circuit consists of four monostable multivibrators 21to 24 cascade coupled through power-d1ivers 25. Each produces a tenmicroseconds pulse. Since the power-drivers function not only to providesufficient power to drive a large number of logic circuits in parallelbut also to invert the pulses, the IL1' to IIA' pulses shown in thesecond graph of FIG. 2 are actually derived from terminals coupled tothe true or l-output sides of the monostable multivibrators. Similarly,the true signals IL1 to lL4 are derived from terminals coupled to thefalse or 0-output sides of the monostable multivibrators.

In a similar manner the timing pulses TP generate the timing levelpulses TLl to TLS' as illustrated in the fourth graph of FIG. 2 throughfive cascaded monostable multivibrators 3l to 35 as shown in FIG. 5. Asnoted hereinbefore, each timing level pulse is five microseconds long.

The reason for designating the positive-going (0 to +6 volts) pulseswith a prime, such as the IL1 and TLl pulses, is that a voltage level of+6 volts is used to represent a bit 0 and a voltage level of 0 volt isused to represent a bit l in the logic of the system to be described.Accordingly, IL1' is to be read as not IL1 while not IL1',

which should be written as I Il-Q is to be read as IL1. To avoidconfusion, the double negative notation will not be used; instead, itscorresponding positive notation is used. However, the inverted or notform of a signal obtained from the false side of a flip-Hop ormonostnble multi vibrator or from the true side through an inverter willvery frequently be used.

The pulses in the last graph of FIG. 2 are derived from an intervalcounter schematically illustrated in FIG. 6. It consists of two cascadedbinary circuits 4l and 42 which count the end of each TL4 pulse andwhich are reset by each IL1 pulse. The function of the interval counteris to separate the binary cells of each half of the drum into digitgroups. Each digit group includes four timing periods, each periodhaving a duration from the end of one TL4 pulse to the end of the nextTL4 pulse. The number of periods in the group has been arbitrarilyselected so that each group may store one four-bit binary-coded decimaldigit. A signal corresponding to each of the interval count periods, ICIto IC4, except the second, IC2, is

obtained from a decoder consisting of three logic AND- gates 43, 44 and45. Inverters 46, 47 and 48 connected to the output terminals of theAND-gates provide the ICI', IC3' and IC4' pulses of FIG. 2.

The sources of these index level, timing level and interval count pulseswill not be referred to again. Instead, input terminals which are to beconnected to particular ones of the output terminals of the circuits inFIGS. 4, 5 and 6 will be indicated by legends.

In addition to the index level and timing level synchronizing pulses,other control signals are obtained from other tracks on the drum. Themanner in which those control signals are derived will be describedhereinafter with reference to FIG. l.

ACCUMULATING SECTION General An ILI pulse gates the inspection data fromthe delay section (not shown) to the accumulating section illustrated inFIG. I. Data transferred to the accommulating section is added duringthe following half drum cycle to data previously accumulated. Forinstance, a bit l denoting that a given type of defect was detected isadded to a previous total in a given accumulator. In the instanternbodiment, there are six data accumulators, one for the total pinholecount, one each for the total number of feet having one of threedifferent types of defects, one for the total number of feet inspectedand one for the total number of prime feet. The accumulating process isrepeated during each half cycle. However, each IL1' pulse gates onlyzero bits into the accumulator section except those lLl' pulses whichfollow a shift operation in the delay section because only then is thereany data being stored in the output shift register and buffer flip-flopsof that section.

Accumulator input control The data from the delay section is gated tothe accumulating section through a bank of AND-gates 300. The outputterminals of the delay section are connected to the input terminals ofthe AND-gates 300 as follows: The total pinhole count to terminals 281to 284; the delayed inspection data to terminals 285, 286 and 265; thebit 1 which represents that a foot of tinplate has been inspected toterminal 294; and the bit which denotes whether the foot to which theinspection data at terminals 285, 286 and 265 pertains is prime toterminal 299. The terminal 299 is coupled to one of the AND-gates 300through an inverter 301 to obtain the complement of the primefoot datasince the logic AND-gate requires the complement or inverted forni ofthe signals to be combined and the prime-foot data, unlike the rest ofthe inspection data, is not presented to the accumulator section of FIG.1 in a complemented form.

Each of th-e output terminals of the AND-gates 300 is connected to a setinput terminal of a different stage of a nine-bit shift register 302. Apair of serial-input terminals 303 are connected to a bit-0 sourceillustrated by a -l-6 volt signal source. Each pulse applied to theshift control terminal 304 of the shift register 302 advances the storeddata one place to the right in order that each bit of the datatransferred in parallel into the shift register may be read out seriallythrough an output terminal 305. As each of the nine bits of data isserially read out, a bit 0 from the serial input terminals 300 isshifted into the shift register. Consequently, as data is seriallyshifted into the accumulators through an AND-gate 306 connected to theoutput terminal 305, the shift register is reset. A manually operatedreset switch MRS connected to the reset input terminal of the shiftregister may be momentarily closed to initially reset the shiftregister.

The data serially read out through the output terminal 305 is gatedthrough the AND-gute 306 by 'IT-MARK pulses which are generated inresponso to T-inarker pulses recorded on a track 307 of the drum 1S.Those pulses arc read by a transducer 308 and translated by an`amplifier 309 to a flip-flop 310 prior to the time of a TL1 pulse. Inthat way the flip-flop 3l0 is set by the time of the leading edge of aTLl pulse and reset by the leading edge of a TL3 pulse applied to itsreset input terminal.

The T-MARK signals from the false output terminal of the flip-flop gatesthe signals from the output terminal 305 to a. binary-coded decimaladder 311 time-shared by the drum accumulators. The T-MARK' pulses arealso applied to the shift control terminal 304 of the shift register 302but since the T-MARK' pulses are positive going (0 to -l-6 volts), thedata in the shift register is not advanced until the negative-going (+6to D volts) trailing edges of the T-MARK pulses are received since theshift register requires negative-going shift control signals.Accordingly, the serial output signal of the shift register is presentedto the binary adder 311 from prior to the time of the leading edge of aTLI pulse to the time of the leading edge of the next TLS pulse. Thenthe Hip-Hop 310 is reset, the AND-gate 306 is disabled, and the data inthe shift register is shifted one place to the right.

In the present embodiment, there are nine T-marker pulses recorded onthe track 307, one for each of the nine bits in the shift register. Thenine T-MARK pulses T1 to T9 time or mark particular binary cells in anaccumulator track 312. Those cells are the rst cells of the sixaccumulators and the second, third and fourth cells of the fifthaccumulator. The following chart graphically illustrates the timing ofthe T-MARK' pulses T1 to T9.

FIRST ACCUMULATOR SECOND ACCUMULATR TH IRD A CC UMULATOR FOURTHACCUMULATOR FIFTH ACCUMULATOR SIXTH ACCL'MULATOR In the foregoing chart,the cells of the six accumiilators are graphically illustrated inseparate lines, but on the drum they would be in one continuous line ortrack. Each cell 1s indicated by either a bit 0 or a bit l. The cellsare separated into groups of four by bars which, of course are notpresent on the drum. In the present embodiment; the. cells are actuallygrouped by the interval counter described with reference to FIG. 6. Theinterval-count signals derived therefrom are utilized in the binaryadder 311 and the data print control circuit of FIG. la to separate thebits sequentially read from cells on the drum into four-bit binary-codeddecimal digits. For instance, the total pinhole count in the fthaccumulator is illustrated in the cart as 0598 in binary-coded decimalform. The least significant digit 8 is stored in the first four cells onthe left of the fifth accumulator and the digit t) in the mostsignilicant decimal order of that number is stored in the last fourcells on the right. Of each group of four cells, the first cell on theleft stores the least significant binary digit. The data is stored inthe accumulator in that order so that the least significant bit of theleast significan digit of each accumulator is always read first as thecells are scanned (from left to right in the chart). That is necessarybecause the binary adder must operate on the binary digits of eachdecimal digit and of the successive decimal digits in the order of theirincreasing signlficance in order that binary carries may be propagatedwithin groups of four cells and decimal carries may be propagatedbetween groups of four cells.

The function of each of the T-MARK' pulses T1 to T9 illustrated in theforegoing chart is to gate one binary digit from the shift register 302to its appropriate accumulator. The first, second, third, fourth andsixth accumulators have only one T-MARK pulse each since they accumulateonly uiitary binary digits. The fifth accumulator, however, has fourT-MARK' pulses T5 to T8 since it accumulates the total number ofpinholes by adding four-bit binary-coded digits which represent thepinholes detected in successive feet of tinplate.

When the accumulated data is printed, in a manner to be more fullydescribed with reference to FIG. la, the last digit of the sixthaccumulator is read out, decoded and printed first because it is themost significant digit of that accumulator and it is desirable to printone digit at a time starting with the most significant digit of the lastaccu mulator. Before that digit is read out, however, an XL signal fromthe flip-flop 319 in the transfer switch 13 (FIG. l) sets azero-suppress circuit in FIG. la which prevents that digit from beingprinted if it is a zero, and prevents all subsequent digits from beingprinted until the tirst nonzero digit is read out and detected. The T9,T5, T4, T3 and T2 pulses are employed for the same purpose when the datafrom the fifth, fourth, third, second and first accumulators are readout and printed in that order. The T1 pulse is used in the print controlcircuit of FIG. la only to determine when al1 of the data has beenprinted.

Drum accumulators The memory portion of each of the accumulatorsconsists of a pair of sectors oppositely disposed on the track 312. Inthe present embodiment, each sector consists of sixteen binary cellswhich are separated into groups of four by interval-count pulses asdescribed hereinbefore.

Referring again to the foregoing chart, it may be seen that the sectorsin one half of the track are arranged in sequence for the sixaccumulators. The last four cells of the sixth accumulator comprise thelast group of four cells on that half of the track before an IL1 pulseresets the interval counter (FIG. 6). The second half of the accumulatortrack 312 is identical to the rst half.

Data stored in a given half of the track is read sequentially by atransducer 313 and a read amplifier 314. A buffer Hip-hop 315 storeseach bit from the amplifier 314 until it is reset by a TLS pulse. In theinterim, a bit stored in the buffer Hip-flop `is translated by thebinary-coded decimal adder to an input terminal of an AND-gate 316 whereit is gated by a TLl pulse to a write amplifier 317 which records thegated bit on the track 312 through a recording transducer 318. In thatmanner, the data is transferred from one side of the track to the othertwice during each drum revolution cycle until a flip-Hop 319 is set totransfer the accumulated data to the buffer section for printing. Thetrue output terminal of the Hip-flop 319 is connected to an inputterminal of the AND-gate 316 so that when it is set, the AND-gate 316 isinhibited.

The hip-flop 319 is set by a shear signal received at a terminal 323from a shear and print command source l2 through an AND-gate 324 when agiven coil inspected is sheared from the line. An IL3' pulse gates theshear signal through the AND-gate 324 to Set the flip-flop 319 at thebeginning of a half drum cycle, All of the data read from the track 312on one side of the drum is then transmitted to the buffer sectionthrough an AND-gate 325 which is enabled by a -l-6 volt signal from thefalse side of the flip-flop 319. The flip-Hop is reset at the beginningof the next half cycle by an IL1 pulse so that accumulation of data fromthe next coil may begin immediately.

While the data read from a given half of the track 312 10 is beingtransmitted through the AND-gate 325 in the transfer switch 13, the datain the other half of the drum is being erased since the write ampliers317 continually records a bit 0 except when it is triggered by a bit 1transmitted through the AND-gate 316.

Data translated through the binary-coded decimal adder 311 is delayedtherein four timing periods. Therefore, if the read head 313 were to beplaced exactly opposite the write head, the data would be shifted orprecessed through four binary cells during each half drum revolution.Accordingly, the write head 318 is slipped ahead in the direction ofrotation through an arc equal to binary cells s0 that it records a bitof data on the track 312 in a cell opposite to the cell read by the readhead 313. In that manner, data read by the head 313 may be translated tothe write head 318 through a four-bit shift register in the binary adder311 and recorded without it precessing around the drum with respect tothe index pulses.

Binary-coded decimal adder Each bit gated through the AND-gate 306 isfed directly to an input terminal 326 of the binary-coded decimal adder311. Each gated bit is also transmitted through an inverter 321 to aninput terminal 327. Hereafter, data fed to the terminal 326 will bereferred t0 as the addend A and the data fed to the terminal 327 will bereferred to as the complement A' of the addend.

Each four-bit binary-coded decimal digit read from the accumulator track312 is fed to an input terminal 328 of the binary-coded decimal adder311. The complement of each bit fed to that terminal is fed to anotherinput terminal 329. Hereafter, data fed to the terminal 328 will bereferred to as the augend B and the data fed to the terminal 329 will bereferred to as the complement B of the augend.

The output signal of the binary-coded decimal adder Will be referred toas the sum, but it should be noted that each bit of the sum fed to theAND-gates 316 and 325 is the complement of the sum as denoted by thelegend SUM'.

The manner in which the addend is added to the augend by the binarycoded decimal adder 311 to provide a binary-coded decimal sum will nowbe described with reference to FIG. 7. In general, the addend is inbinarycoded form but since it consists of either a unitary bit or afour-bit binary-coded decimal digit, the addend `is always abinary-coded decimal digit. The augend is also in binary-coded decimalform because each digit of the augend translated through the adder `is afour-bit, binarycoded decimal digit and the sum is converted to abinarycoded decimal form by the adder. For instance, if two fourbit,binary-coded decimal digits are added in the conventional binary manner,the sum may exceed nine, as when a seven is added to an eight to producea four-brit binarycoded sum of fifteen which has no meaning in abinarycoded decimal system. When that occurs, the sum is converted tothe decimal system by first inserting a carry in the augends next higherorder and then subtracting a binary ten from the forbidden sum, therebyobtaining the binary-coded decimal sum. A ten can be subtracted from theforbidden sum of fifteen by adding to it a binary six and ignoring thecarry.

An example will clarify the foregoing converting process. Assume thatthe augend is 0598 and that the addend is seven. The conventional binaryaddition is as follows:

Carry (D) 0000 000 Augnd l 0000 0101 1001 Addend i)i] P-sum -t 0000 0101i 1001 nii 11 may be inserted into the binary-coded nine of the nextfour binary digits and a six added to the binary-coded fifteen of thefirst four binary digits as follows:

o any 0000 0000 0001 110 Ps0n1 0000 0101 1001 1111 s ix 0110 o-Sum 00000101 i 1010 i 0101 Carry (0)-. l1() o-stnn 1010 0101 stx 0110 sum 0000 i0101 In converting the second digit, the least significant digit is notinvolved since it has already been stored but it has been written againto complete the final sum of 0605.

It should be noted that in the foregoing example the least significantbit of each binary-coded digit has been placed on the right and that aserial adder has been employed so that the binary-coded digits may beadded and converted to the binary-coded decimal system in sequence.

In the binary-coded decimal adder illustrated in FIG. 7, the addendserially presented at terminals 326 and 327 is serially added to theaugend serially presented at terminals 328 and 329. The complement ofthe final sum is then serially presented at an output terminal indicatedby the legend SUM.

The implmentation of the binary-coded decimal adder is illustrated inFIG. 6. It includes a first conventional full adder 33|) to develop thesum of the addend and the augend, bit-by-bit, and to develop a carrysignal whenever any two of the three input signals A, A", B, B; and C, Care equal to a bit l. A complement of the carry signal is gated by aTLZ' to a buffer Hip-flop 331 through an AND-gate 332. The output signalof the flip-flop 331 is transmitted to an AND-gate 333 through anOR-gate 334 until a TLl pulse resets the flip-flop 31. A TL4 pulse gatesthe carry signal to a flip-flop 335 which then generates both a carrysignal C and its complement C' until a TL3 pulse resets it.

The sum developed by the binary adder 330 is serially shifted into afour-bit shift register 340. Four successive TLZ pulses are thereforefed to its shift input terminal in order to shift the four-bitbinary-coded sum into the shift register.

As noted hereinbefore, the sum from the binary adder 330 may exceednine. Consequently, it is necessary to detect when a digit of the sum isany of the forbidden sums from ten to fifteen. A clocked AND-gate 341 isprovided for that purpose. An IC4' clock pulse is required at one of itsinput terminals to insure that an output signal is not transmittedexcept when the four-bit sum to be checked has been properly stored inthe shift register.

If a forbidden sum is present in the four-bit shift register during anIC4 interval, a TL4' ypulse gates a signal through the AND-gate 333 toset the carry flip-op 335, thereby inserting a bit l carry to be addedto the next four-bit binary-coded decimal digit of the augend. Thedecoding logic to determine when there is a forbidden sum stored in theshift register 340 consists of a connection from the false side of thefirst stage to the AND- gate 341 and connections from the true sides ofthe sec- 12 ond and third stages to a third input terminal of the AND-gate 341 through an OR-gate 342.

In that manner, a detected forbidden Sum is partialiy corrected becausea bit l carry has been inserted in the digit of the next higher decimalorder. To complete the correction, a six must be added to the detectedforbidden sum. This is accomplished by gating the complement of thecarry signal from the Hip-fiop 335 through an AND- gate 343 with a TL2pulse during the next ICI interval to set a fiip-op 344. It should benoted that whereas all carries propagated by the first binary adder 330set the carry flip-Hop 335, it is only when the carry Hip-flop 335 isset during an IC4 period that a carry signal C' is gated to theflip-flop 344 to add a six to the forbidden sum.

By the time the fiip-fiop 344 is set, the first bit of the forbidden sumwill have been transmitted through a second binary adder 350 withoutalteration, In effect then, a bit 0 is added to the first bit fed to thebinary adder 350 from the shift register 340. By the time the second bitof the `forbidden sum is fed to the binary adder, the flip-dop 344 isset and a bit l is added to that second bit. The iiip-fiop 344 is notreset until a TL3' pulse gates an ICS signal through an AND-gate 352.Therefore, a bit l is added to the third bit of the forbidden sum fed tothe binary adder. The fourth bit of the forbidden surn is then fed tothe binary adder after the flip-flop 344 is reset. Accordingly, thefourth bit is translated through the adder without alteration unless acarry signal was propagated by the binary adder 350 as a result of a bitbeing added to the third bit of the forbidden sum. In that manner abinary-coded six (0110) is added to the forbidden surn in order tosubtract a ten and thereby correct the sum as explained hereinbefore.

Each carry propagated by the second binary adder 350 is gated through anAND-gate 353 by a TL1 pulse except during the IC4 count interval. Duringthat interval, a t) volt signal is present at a third input terminal ofthe AND- gate 353 which inhibits it from transmitting the carry signalbeing propagated from the most signifiicant bit order of one digit tothe least significant bit order of the next digit when a six is added tocorrect a forbidden sum detected in the shift register.

Each carry signal gated by a TLl pulse through the AND-gate 353 sets abuffer flip-Hop 354. A TL3 pulse then gates the buffer output through anAND-gate 355 to set a carry ip-flop 356. Afterwards, a TL4 pulse resetsthe buffer ip-op 354 and the following TLZ pulse resets the carryHip-flop 356 to clear the carry signal.

If the sum of two digits is sixteen, seventeen or eighteen, only part ofthe forbidden sum is stored in the shift register, the other part beinga carry propagated during an IC4 interval when the most significant bitsof the addend and augend are added in the first binary adder 330. Thepart that is stored in the shift register will be equal to either zero,one or two depending upon Whether the sum is sixteen, seventeen oreighteen. None of those parts appear as forbidden sums; instead, theyappear as proper binary-coded decimal digits. Therefore, the decodingAND-gate 3411 will not initiate the addition of six necessary to correctthe second part of a forbidden sum stored in the shift register.However, the forbidden sum will nevertheless be automatically correctedbecause the carry propagated by the addition of the most significantbits in the first binary adder 330 is gated frorn the carry ilipop 335through the AND-gate 343 by a TLZ' pulse during the next IC1' intervalto initiate the addition of six in the second binary adder 350.Correction of each of the forbidden sums sixteen, seventeen and eighteenis then accomplished by the addition of six to the part stored in theshift register in order to obtain the sum of six, seven and eight,respectively. The other part of the correcting process, namely thepropagation of a carry to the next higher decimal order is accomplishedby adding the carry signal output of the tlip-op 355 to the first bit ofthe digit in the next higher order.

13 BUFFER SECTION As noted hereinbefore with reference to FIG. 1, datais accumulated in the accumulator section until a shear command isreceived. During a following complete half drum cycle, all of the datais transferred to a drum buffer 14 where it is stored until it is neededby the printer 16 for the preparation of a permanent record.

Drum buffer The manner in which the drum buffer is implemented isillustrated in FIG. 1. It consists of a plurality of sectors arranged inpairs around the drum 18 on a track 370 in the same manner as theaccumulator sectors on the track 302. When the transfer flip-flop 319 inthe transfer switch 12 is set by the coincidence of a shear signal andan IL3' pulse at the AND-gate 324, the AND-gate 316 is disabled. TheAND-gate 325 is then enabled to transmit the data from the adder 311 tothe buffer track 370 during the next half cycle, after which theflip-flop 319 is reset by an ILl pulse and the accumulation of new datafrom the next coil inspected begins in the accumulating section.

Each bit of data from the AND-gate 325 is gated by a TL1 pulse throughan AND-gate 371 to a write amplifier 372 and its associated recordingtransducer 373. Since the transfer of data will always start at thebeginning of a half drum cycle, it is completed in one half of a drumcycle. During the next half drum cycle, the transferred data recorded onone half of the buffer track 370 is read by a transducer 374 andamplifier 375.

Each bit of data read is stored in a buffer flip-flop 376 from a timeprior to a TLl' pulse until a TLZ pulse r:- sets it. The complement ofeach bit stored in the buffer flip-flop is transmitted through anAND-gate 377 which is connected to an output terminal 378 of theHip-flop 376 and enabled by the true side of the flip-flop 319 which hasbeen reset by an ILl pulse at the beginning of the next cycle. Theoutput signals from the AND-gate 377 are transmitted through an OR-gate379 to the ANDgate 371 and gated by TLl pulscs to the write amplifier372. Once the accumulated data has been transferred to the buffer track370, the accumulation of data on the track 312 may be resumed while datain the buffer track 370 is printed out.

Data print control The function of the data print control circuitillustrated in FIG. 1a is to present the data in the drum buffer (FIG.l) to a printer 16 in serial fashion. In order to identify particulardigits, reference will be made to certain accumulators even though thedata to be printed has been transferred to the drum buffer. Thus, aparticular digit will be identified by the accumulator from which it hasbeen transferred` In printing data from the drum, the most significantdigit of the sixth accumulator is printed first followed by the lesssignificant digits, in order, until all four digits have been printed.This process is then repeated for the fifth, fourth. third, second andfirst accumulator, in order. All of the data is printed on a sheet ofpaper from left to right on a single line so that the most significantdigit of each accumulator will appear on the left. The data may beidentified by its relative position in the line. Vertical lines may beprovided on the sheet at intervals of four spaces to separate the data.When the least significant digit of the first accumulator has beenprinted, the printer is turned off and the print control circuit isreset to its initial condition.

The presentation of data to the printer 16 is controlled by an AND-gate401 which, when enabled, transmits TL2' pulses to the shift inputterminal of a four-bit shift register 402, the serial input terminals ofwhich are connected to the output terminal 378 of the buffer Hip-Hop 376in the drum buffer (FIG. l). The AND-gate 401 transmits four successiveTL2' pulses to the shift register 14 each time a digit to be printed isread from the buffer into the shift register.

The signal at the terminal 378 is the complement of a given bit storedin the buffer flip-flop 376. Accordingly, the terminal 378 is connecteddirectly to the false input terminal of the shift register 402 and iscoupled by an inverter 403 to its true input terminal. The function ofthe shift register is to convert each four-bit digit to be printed fromtime sequential information to static parallel information.

Each static four-bit digit is transmitted in parallel from the shiftregister 402 to the printer by a network 404 which may include a codeconverter if one is neces sary in order to operate the printer 16. Inthe present embodiment, it is assumed that the printer is electronicallyoperated with the 8, 4, 2, l code employed throughout for thebinary-coded decimal digits. Therefore, the net work 404 transmits eachbit of a given digit to the printer through separate parallel channels,each channel including a two-input AND-gate. One input terminal of eachAND-gate is connected to an output terminal 405 of the printer 16. Acam-actuated switch delivers a +6 volt signal to the terminal 405 whenthe printer has com pleted printing a digit and is in its position ofrest. When that +6 volt signal is present, the gated transmittingnetwork 404 translates the signals of the next digit read out to theprinter.

The network 404 is provided with a fifth channcl which also includes atwo-input AND-gate having one input terminal connected to the falseoutput terminal of a zero suppress flip-flop 406 and the other inputterminal connected to the terminal 405. The function of that fiip-op isto provide a fifth bit to be translated to the printer when a digit isto be printed. That bit is normally a bit 0 which may always be ignoredwhile printing any digit. However, if the flip-flop 406 has been set toinsert a bit l and the digit to be printed is the binary code 000() forthe digit zero, the bit l inserted provides the binary-coded word 00001,which is a coded instruction to be used for causing the printer toadvance one space without printing, thereby suppressing a zero. In thepresent embodiment, all zeroes which occur before the first non-zerodigit of the data to be printed from a given accumulator are suppressed.

Signals from the shear and print command source 12 (FIG. 1) initiate theprocess of printing the accumulated data. For simplicity, the shearcommand source is illustrated in FIG. 1a as a switch 410 which ismomentarily closed to set a ip-fiop 411 and thereby transmit a +6 voltSHEAR signal to the output terminal 323. That signal actuates thetransfer switch 13 (FIG. l) to cause the accumulated data to betransferred to the drum buffer as described hereinbefore and toinitially set the zero-suppress flip-fiop 406 by a signal XL transmittedfrom the false side of the flip-fiop 319 (FIG. 1) through an inverter407.

The process of transferring data to the drum buffer requires at most onedrum revolution cycle which may be assumed to be about 33% millisecondsin the present embodiment. Accordingly, the automatic printing of datafrom the buffer drum may begin almost immediately. However, provision ismade for first manually printing such information as the coil number andthe customers order number.

Momentarily closing the switch 410 also sets a flipflop 412 and resets aflipflop 413. The function of the flip-flop 412 is to turn on theprinter. Data may then be manually printed. The function of theflip-flop 413 is to reset the flip-Hop 412 when the automatic printingof the drum data is complete in order to turn the printer off.

When the manual printing has been completed, a switch 414 is momentarilyclosed to enable an AND-gate 415. The next IL1' pulse is thentransmitted through the en- 15 abled AND-gate to reset the iiip-flop 411and initiate the automatic printing of the drum data.

Before the Hip-flop 411 is reset, however, an ILl' pulse is gatedthrough an AND-gate 421 to reset a tiip-iiop 422 previously set upon thecompletion of the automatic printing of drum data pertaining to the lastcoil sheared from the line. The function of that flip-hop is to enablean AND- gate 423 when it is set after the last digit to be printed hasbeen read out of the drum buffer into the shift register 402. When theprinting of the last digit has been cornpleted and the cam-actuatedswitch produces a +6 volt signal at terminal 40S, the AND-gate 423transmits a signal to set the flip-flop 413 which in turn resets theflip-iiop 412 and turns the printer oli.

The SHEAR signal also enables an AND-gate 424 which transmits an IL3'pulse to a flip-Hop 425 which had been set upon the completion of thelast printing cycle by a signal transmitted through an AND-gate 426. Thefunction of the AND-gate 426 is to detect when the last digit to beprinted has been read into the shift register 402. That digit is thefirst or least significant digit of the first accumulator. When theflip-flop 425 is set, a print-complete signal PC' is transmitted to oneof three input terminals of an AND-gate 427 via a lead not shown.

The function of the AND-gate 427 is to transmit an IL2 pulse to the setinput terminal of the flip-flop 422. However, a fetch-digit controlsignal FD' is required at the third input terminal of that AND-gatebefore an ILZ' pulse may be transmitted to set the Hip-flop 422 andinitiate the steps necessary to turn the printer off. The manner inwhich the fetch-digit signal is produced will be dcscribed as thedescription of a printing cycle progresses.

A third AND-gate 430 is also enabled by the SHEAR signal at terminal 323to transmit a TL4 pulse to the set input terminal of thc first stage ofa binary counter 431, thereby incrementing it to one. TLS' pulses aretransmitted through an AND-gate 432 which is also enabled through anOR-gate 433 by the true output signal of the set flipfiop 411, therebyinitially resetting the counter 431 to zero. Acordingly, as long as thefiip-tiop 411 is set, the first stage is continually set and reset.

The next IL1 pulse to occur after the switch 414 is closed resets thetiip-op 411 and disables the AND-gates 421, 424, 430 and 432. Theflip-flops 422 and 425 remain reset and the first stage of the binarycounter 431 remains set since the last TL4' pulse in a given half drumcycle sets it, and the next resetting TLB' pulse is not transmitted tothe AND-gate 432 until after the lLl' pulse has reset the flip-flop 411and disabled the AND-gate 432. In that manner, an extra bit l isinserted in the binary counter 431 when the automatic printing processis begun by the cincidence of an 11.1' pulse and the momentary closureof the switch 414.

That bit is denominated an extra bit because the counter is normallyadvanced by TL2 pulses which occur during IC4 intervals in order tolocate a given digit to be counted. The function of that extra bit is topermit the counter to address the digit stored in the l22nd sector byreaching a count of 122 while the 121st digit sector is being scanned,assuming that there are l22 digit sectors on each half of the buffertrack 370 (FIG. l) and not the more limited number of sectorsillustrated in the foregoing chart.

The function of the counter 431 itself will now be more fully described.It is to be recalled that each digit sector is capable of storing afour-bit binary-coded digit and it is assumed that digits are actuallystored in only the last twenty-four sectors. The counter will locate thefirst digit to be read out of the l22nd sector by counting to 122. Sincean extra bit was inserted initially, the counter will reach the count of122 when the l2lst sector is being scanned. An AND-gate 435 is thenenabled by output signals from the counter. A subsequent TL4' pulse istransmitted through the enabled AND-gate 435 to the fiip-op 436, therebysetting it to initiate the generation of a readout control signal if thecani-actuated switch in the printer 15 is transmitting a +6 volt signalat terminal 405. lf it is, the digit in the l22nd sector is read intothe shift register 402 and printed in a manner to be more fullydescribed; if not, the digit in the l22nd sector is not read into theshift register for printing. In either event, the counter is reset tozero when the first cell of the 122nd sector is scanned.

If the digit in the 122nd sector is not printed, the counter will begincounting again as that sector is being scanned. Accordingly, the countof l22 will be reached again while the l21st sector on the other side ofthe buffer track is being scanned. In that manner, the l22nd sector ofalternate halves of the buffer track will continually be addressed untilit is read out and printed.

After the digit in the l22nd sector is printed, the counter must addressthe l2lst sector by again reaching the count of 122. To acomplish that,another extra bit is inserted while the l22nd sector is being scanned.Thereafter, as the normal counting procedure is resumed while the l22ndsector is still being scanned, the counter will be advanced until itreaches the count of 122 during the 120th sector. If a -|-6 volt signalis then present at terminal 405, the l21st digit is read out, a thirdextra bit is inserted and the counter is subsequently advanced to l22while the 119th sector is being scanned in order to read out the 120thdigit.

In that manner, each digit stored is addressed in inverse sequence, at arate determined by the printer, by always counting 121 sectors relativeto the last one read out and printed. The processing of the address iscontinued by inserting an extra bit l each time a digit is printed untilall of the twenty-four digits stored have been printed. When the lastdigit stored has been printed, the address will again be preeessed tothe next digit sector, but since a digit is not stored in that sector,the completion of the automatic printing process is detected and theprinter is turned off.

The manner in which the foregoing is accomplished will now be describedin detail. The counter 431 is driven by TL2' pulses transmitted throughan AND-gate 440 when enabling IC4 pulses are transmitted to a secondinput terminal of the AND-gate 440 through an OR-gate 441. An inverter442 couples the AND-gate 40 to the input terminal of the counter 431 inorder to provide positive-going pulses to the steering circuit of thefirst binary stage of the counter.

Since the first stage of the counter was set by a TL4' pulse, the rstTLZ' pulse gated by the first IC4 signal advances the count to two.Referring brieliy to FIG. 2, the following may be readily understood;(l) that the first TL2' pulse gated to the counter is the fifth TLZ'puise in the half drum cycle following the ILl pulse which resets theiiip-fiop 411 to begin the automatic printing process; (2) that thesecond, third, fourth and tifth TIA pulses mark the cells of the firstfour-bit digit memory sector on the buffer track; and (3) that the firstTLZ' pulse gated to the counter occurs at the end of the tirst digitlocation. Accordingly, the counter is advanced to two approximatelytwenty-five microseconds before the lirst bit of the second digit isscanned. Each TLZ.' pulse gated by subsequent IC4 signals advances thecounter until the count of 122 is reached twenty-five microsecondsbefore the first cell of the l22nd digit sector is scanned.

When the count of l22 is reached, the AND-gate 435 is enabled. Tenmicroseconds later, a TIA pulse is transmitted through the enabledAND-gate 435 to set the flip-liep 436, thereby enabling an AND-gate 445.An ICI' pulse is then transmitted to the AND-gate 432 via the OR- gate433 to gate the next TL3 pulse to the reset input terminal of thecounter 431. In that manner, the counter is reset while the first binarycell of the 122ml digit is being scanned.

If the printer had not been free to print a digit at the beginning ofthe half drum cycle during which the l22nd digit was located, a |6 voltsignal would not have been transmitted from the terminal 405. Therefore,an IL2 pulse would not have been gated to a liip-fiop 446 through anAND-gate 447 and the hip-flop 446 would not have been set to produce afetch-digit control signal FD'. Accordingly, an AND-gate 448 would nothave been enabled and a read-out control signal would not have beentransmitted through an inverter 449 to the read-out control AND-gate 401in order to gate four TL2' pulses while the four binary cells of the122ml sector are being scanned.

Under those conditions, the l22nd digit is not read into the shiftregister 402 and the binary counter, after first being reset by a TLSpulse, continues to count all subsequent TL2 pulses which occur during1C4 intervals. Upon again reaching the count of 122, the counter againlocates the 122nd digit in the same manner as before. lf the fetch-digitsignal FD' is then present, the four-bits of the 122nd digit are readfrom the other half of the drum. Assuming that a fetch-digit signal FDis present when the flip-flop 436 is set. the AND-gate 448 transmits areadout control signal to the AND-gate 401.

It should be noted that the flip-flop 425 remains reset because the onlyway in which it can be set is by having both flip-flops 436 and 450 setat the same time to enable an AND-gate 426. That cannot occur untilafter the least significant digit of the rst accumulator in the 99thdigit location has been printed. At that time the address will precessto the 98th digit location and the count of 122 will be reached when thelast cell of the 97th digit is being scanned. A TL4' pulse transmittedduring that period sets the flip-flop 436. By then, the flip-flop 450has been set by an Il I pulse but not reset because the first T-MARKpuise T1 does not occur for at least five microseconds. Accordingly, theAND-gate 426 transmits a signal to the flip-flop 425 and resets it,thereby disabling the AND-gate 448. However, while locating the 122mldigit, the print-complete circuit does not function because the Hip-liep450 is reset and the Hip-flop 425 is not Set. Accordingly, a read-outcontrol signal is transmitted to the AND-gate 401 to enable it totransmit four succes sive TL2' pulses which shift the four-bit digitfrom the l22nd location into the shift register 402.

The zero-suppress filip-Hop 406, initially set by an XI.' pulse, isreset by the first nonzero digit of the sixth accumulator in a manner tobe described. It is set again by the first digit to be printed from eachsubsequent accumulator. For instance, assume that the 118th digit sectoris addressed. The read-out control signal enables an AND- gate 455 andan AND-gate 456. The T-MARK pulse T9 which now occurs four cell periodsearlier with respect to the stored data, is transmitted through theenabled AND-gate 455 and the flip-flop 457 is set. Its false outputsignal transmitted through the enabled AND-gate 456 sets thezero-suppress flip-Hop 406, the true output signal of which resets theHip-flop 457,

The true output signals from each stage of the shift register areconnected to input terminals of an OR-gate 458. lf each bit of thefour-bit digit stored in the shift register is a bit 0, all of thesignals to the OR-gate are +6 volt signals. Accordingly, its outputterminal remains at t) volts and an AND-gate 459 remains disabled.

A signal transmitted by an AND-gate 460 sets a fliptlop 461 whichtransmits a print signal to the printer and the AND-gate 459. However,because the AND-gate 459 is not enabled, a signa] is not transmitted toreset the liipA flop 406. Accordingly, the hip-Hop 406 inserts a bit linto the network 404 and a space or blank is provided on the recordinstead of a zero to suppress the printing of a zero.

The AND-gate 460 does not transmit a signal to the print control ip-op461 until after a flip-flop 462 is set and the flip-flop 436 is reset.The former is set by the first TLZ pulse gated through the AND-gate 401.The latteris reset by a TLS pulse transmitted through an AND-gate 463during the IC4 interval, which is during the next timing level periodfollowing the TL2 pulse which shifts the 18 fourth bit of the digit tobe printed into the shift register.

In the interim, the false output signal from the set flipilop 436enables the AND-gate 445 to transmit an ICI' pulse via the OR-gate 433to the AND-gate 432. A TL3' pulse is thereby gated to the reset inputterminal of the counter 431 and the counter is reset.

When the flip-flop 436 is reset, the read-out control signal is removed,and AND-gate 401 is disabled and no further TL2 pulses are transmittedto the shift register 402. Thus, the flip-flop 436 is set to provide aread-out control Signal if the fetch-digit signal FD is present from thetime of a TIA pulse of the IC4 interval preceding the location of thedigit to be printed out until the time TLS pulse of the IC4 interval ofthe digit read out for printing. Referring again to the fourth and fifthgraphs of FIG. 2. it may be readily seen that only four TL2' pulsesoccur while the flip-flop 436 is set.

Before the flip-flop 436 is reset, the read-out control signal gates anICS signal through an AND-gate 464. That signal is transmitted to theAND-gate 440 through the OR-gate 441 to gate a TL2' pulse to the binarycounter 431, thereby inserting an extra bit which causes the counter tolocate the next digit to be printed out. Subsequent TLZ' pulses gated byIC4 signals via the OR-gate 441 advance the counter to 122. Due to theextra bit inserted while the 12lst digit sector was being scanned andthe 'f1.2' pulse counted while the l22nd digit sector was being read outinto the shaft register, the counter reaches the count of 122 while the120th digit sector on the other side of the buffer track 370 (FIG. l) isbeing scanned.

Even the fastest printer available could not complete the printing ofthe first digit by the time the second digit is located .on the otherside of the buffer track. Accordingly, the counter is reset severaltimes by TLS pulses dur-- ing an lCl interval of the lllst digit sectorand again advanced to 122 by TLZ' pulses. However, since a rendoutsignal is not being transmitted to the AND-gate 464 each time the countof 122 is reached, extra TL2' pulses are not inserted again.Accordingly, the counter continually addresses the l21st digit until afetch-digit control FD' signal is present.

When the printing of the first digit has been cornpleted, a +6 voltsignal is transmitted from the terminal 405 to a one-shot circuit 466which in turn resets the print control flip-flop 461 and the flip-flop462. The latter resets the shift register 402 through an inverter 463.

The +6 volt signal at the terminal 405 also enables the AND-gate 447 asdescribed hereinbefore. The next ILZ' pulse, therefore, sets theflip-flop 446 via the AND- gate 447. Accordingly, when the l2lst digitis again located, a read-out control signal is transmitted to theAND-gate 401 and the 121st digit is read out for printing.

If the 121st digit is not a zero, the AND-gate 459 is enabled and theprint signal, generated in the same manner as before, resets theflip-flop 406. The nonzero digit is then printed. After the printing ofthat digit is complete, the cycle is repeated for the next two digits ofthe sixth accumulator, both of which are printed whether or not they arezeroes because the zero-suppress ipflop 406 has `been reset.

The drum data from each of the remaining accumulators is printed in asimilar manner. For instance, when the most significant digit of thedata from the fth accumulator is located and read into the shiftregister 402, the T-MARK' pulse T9 which now occurs while the first cellof that digit is being scanned, sets the zero-suppress hip-flop 406. Thefirst nonzero digit to be read into the shift register thereafter resetsit and all subsequent digits from that accumulator are printed.

After the least significant digit of the first accumulator (the 99thdigit), has been located and read into the shift register 402, thecounter will locate the 98th digit by setting the flip-flop 436 Whilethe 97th digit is being 19 addressed. The AND-gate 426 then transmits asignal for the lirst time because, as described hereinbefore, theflip-op 450 set by the last ILl pulse has not been reset by a T1 pulse.Accordingly, the flip-flop 42S transmits a print complete signal PC' tothe AND-gate 427.

When the printing of the least significant digit of the firstaccumulator has been completed, a fetch-digit signal FD' is produced.However, a read-out signal is not produced again because the AND-gate448 is no longer enabled since the Hip-flop 425 has been set.

The fetch-digit signal FD' is transmitted to an input terminal of theAND-gate 427 by a lead not shown.

When the printing of the least significant digit of the With both the PCand FD' signals present, the AND-gate 427 is enabled and the next lL2pulse is transmitted to the ilip-fiop 422. The AND-gate 423 is enabledby a digitneeded signal at the terminal 40S. Accordingly, when theflip-op 422 is set by an IL2 pulse via the ANDgate 427, the flip-flop413 is set, the flip-Hop 412 is reset and the printer is turned ofi,thereby completing one full printing cycle for all of the datapertaining to a given coil.

While the principles of the invention have now been made clear in anillustrative embodiment, there will be immediately obvious to thoseskilled in the art many modifications in structure, arrangement,proportions, the elements, materials, and components, used in thepractice of the invention, and otherwise, which are particularly adaptedfor specific environments and operating requirements, without departingfrom those principles. The appended claims are therefore intended tocover and embrace any such modifications, within the limits only of thetrue spirit and scope of the invention.

What is claimed is:

l. In a system for storing a plurality of data items in a correspondingplurality of memory locations accessible in a predetermined order,apparatus for transferring the data items in sequence from the memorylocations to a utilization means in the inverse order comprising:reading means for periodically scanning the memory locations in thepredetermined order, counter means for storing a count, means formodifying the count in said counter means by a predetermined quantityfor each memory location scanned by said reading means, transfer meansresponsive to a predetermined count in said counter means fortransferring to the utilization means the data item in the memorylocation having a predetermined relationship with said reading means`and means responsive to the predetermined count in said counter meansfor causing the count in said counter means to equal the predeterminedquantity, whereby said transfer means causes the data item in the nextpreceding memory location to be transferred to the utilization meansduring a subsequent periodic scanning of the memory locations by saidreading means.

2. In a system for storing a plurality of data items in a correspondingplurality of memory locations accessible in a predetermined order,apparatus for transferring the data items in sequence from the memorylocations to a utilization means in the inverse order comprising:transducer means for periodically scanning the memory locations in thepredetermined order and for reading the data item from each memorylocation as it is scanned, counter means for storing a count, meansconnected to said transducer means for modifying the count in saidcounter means by a predetermined quantity for each memory locationscanned by said transducer means, transfer means responsive to apredetermined count in said counter means for transferring from saidtransducer means to the utilization means the data item in the memorylocation having a predetermined relationship with said transducer means,and means responsive to the predetermined count in said counter meansfor causing the count in said counter means to equal the predeterminedquantity, whereby said transfer means in response to the count in saidcounter means transfers the data item in the next preceding memorylocation from said transducer means to the utilization means during asubsequent periodic scanning of the memory locations by said transducermeans.

3. In a system for storing data items in n storage locations accessiblein a predetermined order, apparatus for transferring the data items insequence from the memory locations to a utilization means in the inverseorder comprising: reading means for periodically scanning the storagelocations in the predetermined order, counter means for storing a count,incrementing means for incrementing the count in said counter means byone for each storage location scanned by said reading means, transfermeans responsive to a count of n in said counter means for transferringto the utilization means the data item in the storage location having apredetermined relationship to said reading means, and means responsiveto the count of n in said counter means and to the transfer of a dataitem to said utilization means for reducing the count in said countermeans to a count of one be* fore said counter means is incremented bysaid incrementing means while said reading means scans the next storagelocation, whereby said counter means causes said transfer means totransfer the data item in the next preceding storage location to theutilization means during a subsequent periodic scanning of the storagelocations by said reading means.

4. In a system for storing data items in n memory locations accessiblein a predetermined order, apparatus for transferring the data items insequence from the memory locations to a utilization means in the inverseorder comprising: reading means for periodically scanning the memorylocations in the predetermined order, counter means for initiallystoring a count of one, incrementing means for incrementing the count insaid counter means by one for each memory location scanned by saidreading means, transfer means responsive to a count of n in said countermeans for transferring to the utilization means the data item in thenext memory location to be scanned by said reading means, meansresponsive to the count of n in said counter means for reducing thecount in said counter means to a count of one before said counter meansis incremented by said incrementing means while said reading means scansthe next memory location in the predetermined order, whereby saidcounter means causes said transfer means to transfer the data item inthe next preceding memory location to the utilization means during asubsequent periodic scanning of the memory locations by said readingmeans.

5. In a system for storing data items in a plurality of storagelocations accessible in a predetermined order, apparatus fortransferring the data items in sequence from the memory locations to autilization means in the inverse order comprising: reading means forperiodically scanning the storage locations in the predetermined order,counter means for storing a count, incrementing means for incrementingthe count in said counter means by one for each storage location scannedby said reading means, transfer means responsive to a predeterminedcount in said counter means for normally transferring to the utilizationmeans the data item in the storage location having a predeterminedrelationship to said reading means, means responsive to thepredetermined count in said counter means and to the transfer of a dataitem to the utilization means for reducing the count in said countermeans to a count of one before said counter means is incremented by saidincrementing means while said reading means scans the next storagelocation, and means responsive to the predetermined count in saidcounter means and to the absence of a transfer of a data item to theutilization means for reducing the count in said counter means to acount of zero before said counter means is incremented by saidincrementing means while said reading imeans scans the next storagelocation.

6. In a system for sequentially operating on data stored in n memorylocations accessible in a predetermined cyclical order, apparatus forsequentially reading out stored data in inverse order comprising: atransducer for reading said data from said memory locations in apredetermined cyclical order, means for counting said memory locationsas they are read during a given cycle, means for initially incrementingsaid counting means to the count of one, decoding means for detectingwhen said counting means reaches the count of n, translating meanscoupled to said transducer and decoding means for transmitting data readfrom the next memory location in response to decoding the count of n,means for resetting said counting means before data from the next memorylocation is read and counted, and means for further incrementing saidcounting means to the count of two as data is read out of the nextmemory location, whereby the counting means causes data in the nextpreceding :memory location to be read out during a subsequent readingcycle.

7. In a buffer system for storing n binary-coded digits in a cyclicalmemory system until a means for preparing a permanent record is ready toaccept the digits, one at a time in inverse order, the combinationcomprising: a transducer for scanning said digits; means for countingsaid digits as they are scanned in sequence, means for initiallyincrementing said counting means to the count of one, decoding means fordetecting when said counting means reaches the count of n, means forreading out the next digit in response to the coincidence of decodingthe count of n and receiving a signal from said means for preparing apermanent record indicating that it is ready to accept the next digit,means responsive to a count of n in said counting means for resettingsaid counting means before said next digit is read out and counted, andmeans responsive to acceptance of a digit from said memory system bysaid means for preparing a permanent record for further incrementingsaid counting means to the count of two with another pulse when saidnext digit is read out, whereby the counting means will address the nextpreceding digit during the next memory cycle by again counting n digitsif a digit is not read out during the current memory cycle, and willcontinue to address the next digit during subsequent memory cycles bycounting n digits until it is read out, at which time the counter isincremented to the count of two with another pulse to address the nextpreceding digit during the following memory cycles until the nextpreceding digit is read out.

8. In a system for storing a plurality of data items in a correspondingplurality of memory locations accessible in sequence in a predeterminedorder, control apparatus for controlling the transfer of data items insequence from the memory locations to a utilization means in the inverseorder comprising: reading means for periodically scanning the memorylocations in sequence in the predetermined order, counter means forstoring a count, means for changing the count in said counter means by apredetermined quuntity for each memory location scanned by said readingmeans, transfer means responsive to a predetermined count in saidcounter means for transferring to the utilization means the data item inthe memory location having a predetermined relationship with saidreading means, and means responsive to the transfer of a data item froma memory location to the utilization means for causing said change meansto provide an extra change in the count in said counter means, wherebythe control apparatus causes the data item in the next preceding memorylocation to be transferred to the utilization means during the nextperiodic scanning of a memory location by said reading means.

9. In a system for storing a plurality of data items in a correspondingplurality of memory locations accessible in sequence in a predeterminedorder, control apparatus for controlling the sequential transfer of dataitems from the memory locations to a utilization means in the inverseorder comprising: reading means for periodically scanning the memorylocations in the predetermined order, counter means for counting thenumber of memory locations scanned by said reading means commencing withan initial count, transfer means responsive to a predetermined count insaid counter means for transferring to the utilization means the dataitem in the memory location having a predetermined relationship withsaid reading means, means responsive to the predetermined count in saidcounter means for changing the count in said counter means to theinitial count, and means responsive to the transfer of a data item tothe utilization means for causing said counter means to record an extracount, whereby the control apparatus causes the data item in the nextpreceding memory location to be transferred to the utilization meansduring a subsequent periodic scanning of the memory locations by saidread` ing means.

10. In a system for storing a plurality of data items in a correspondingplurality of memory locations accessible in sequence in a predeterminedorder, control apparatus for controlling the sequential transfer of dataitems from the memory locations to a utilization means in the inverseorder comprising: reading means for periodically scanning the memorylocations in the predetermined order, counter means for counting thenumber oi memory locations scanned by said reading means commencing withan initial count, signal means connected to the utilization means forproviding a signal when the utilization means is ready to receive a dataitem, transfer means responsive to a predetermined count in said countermeans and to the signal provided by said signal means for transferringto the utilization means the data item in the memory location having apredetermined relationship with said reading means, means responsive tothe predetermined count in said counter means for changing the count insaid counter means to the initial count, and means responsive to thetransfer of a data item to the utilization means for causing saidcounter means to record an extra count, whereby the control apparatuscauses the data items in successively preceding memory locations to betransferred to the utilization means as the utilization means acceptsdata items during subsequent periodic scans of the memory locations bysaid reading imeans.

References Cited UNITED STATES PATENTS 2,853,696 9/1958 Mendelson340--173 2,983,904 5/l96l Moore B4G-172.5 3,069,666 12/1962 AustinS40-174.1

BERNARD KONICK, Primary Examiner.

TERRELL W. FEARS, Examiner.

1. IN A SYSTEM FOR STORING A PLURALITY OF DATA ITEMS IN A CORRESPONDINGPLURALITY OF MEMORY LOCATIONS ACCESSIBLE IN A PREDETERMINED ORDER,APPARATUS FOR TRANSFERRING THE DATA ITEMS IN SEQUENCE FROM THE MEMORYLOCATIONS TO A UTILIZATION MEANS IN THE INVERSE ORDER COMPRISING:READING MEANS FOR PERIODICALLY SCANNING THE MEMORY LOCATIONS IN THEPREDETERMINED ORDER, COUNTER MEANS FOR STORING A COUNT, MEANS FORMODIFYING THE COUNT IN SAID COUNTER MEANS BY A PREDETERMINED QUANTITYFOR EACH MEMORY LOCATION SCANNED BY SAID READING MEANS, TRANSFER MEANSRESPONSIVE TO A PREDETERMINED COUNT IN SAID COUNTER MEANS FORTRANSFERRING TO THE UTILIZATION MEANS THE DATA ITEM IN THE MEMORYLOCATION HAVING A PREDETERMINED RELATIONSHIP WITH SAID READING MEANS,AND MEANS RESPONSIVE TO THE PREDETERMINED COUNT IN SAID COUNTER MEANSFOR CAUSING THE COUNT IS SAID COUNTER MEANS TO EQUAL TO THEPREDETERMINED QUANTITY, WHEREBY SAID TRANSFER MEANS CAUSES THE DATA ITEMIN THE NEXT PRECEDING MEMORY LOCATION TO BE TRANSFERRED TO THEUTILIZATION MEANS DURING A SUBSEQUENT PERIODIC SCANNING OF THE MEMORYLOCATIONS BY SAID READING MEANS.